HDL Reference Guide

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HDL Reference Guide

(last edit: 16. January 2022)

Introduction
Using this Guide
Alphabetical Reference

Introduction

This HDL Reference Guide is a combined quick reference guide to the VHDL language, the Verilog Language and the SystemVerilog Language its syntax, semantics, synthesis and application to hardware design.

This Reference Guide shows examples of all three languages and compares the different ways of constructing the functionality. It is not intended as a replacement for the IEEE Standard HDL Language Reference Manuals. Unlike these documents, this Reference guide does not offer a complete, formal description of HDL. Rather, it offers answers to the questions most often asked during the practical application of HDL, in a convenient reference format.

Nor is The HDL Reference Guide intended to be an introductory tutorial. Information is presented here in a terse reference format, not in the progressive and sympathetic manner necessary to learn a subject as complex as VHDL. However, acknowledging that those already familiar with computer languages may wish to use this guide as a VHDL text book, a brief informal introduction to the subject is given at the start.

The main feature of The HDL Reference Guide is that it compiles information regarding VHDL, Verilog and SystemVerilo into an easy to use page with examples and comparisons to aide the HDL designer working in shifting environments and shifting languages.

Using this Guide


Alphabetical Reference

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

A	VHDL	SystemVerilog	Verilog
		Abs
		Access
	Aggregate
	Alias
	Architecture
	Array
	Assert
	Attribute
	Attribute Name
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B	VHDL	SystemVerilog	Verilog
	Block
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C	VHDL	SystemVerilog	Verilog
	Case
	Coding Standards
	Component
	Concurrent Statement
	Conditional Assignment
	Configuration
	Configuration Specification
	Constant
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D	VHDL	SystemVerilog	Verilog
	Data Type
	Declaration
	Design Flow
	Disconnect
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E	VHDL	SystemVerilog	Verilog
	Entity
	Enumeration
	Errors
	Exit
	Expression
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F	VHDL	SystemVerilog	Verilog
	File
	File (Vhdl)
	Floating
	For Loop
	Function
	Function Call
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G	VHDL	SystemVerilog	Verilog
	Generate
	Generic
	Generic Map
	Group
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H	VHDL	SystemVerilog	Verilog

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I	VHDL	SystemVerilog	Verilog
	If
	Instantiation
	Integer
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J	VHDL	SystemVerilog	Verilog

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K	VHDL	SystemVerilog	Verilog

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L	VHDL	SystemVerilog	Verilog
	Library
	Loop
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M	VHDL	SystemVerilog	Verilog
	Math
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N	VHDL	SystemVerilog	Verilog
	Name
	New
	Next
	Null
	Number
	Numeric_Std
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O	VHDL	SystemVerilog	Verilog
	Operator
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P	VHDL	SystemVerilog	Verilog
	Package
	Physical
	Port
	Port Map
	Procedure
	Procedure Call
	Process
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Q	VHDL	SystemVerilog	Verilog
	Qualified Expression
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R	VHDL	SystemVerilog	Verilog
	Range
	Record
	Report
	Reserved Words
	Return
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S	VHDL	SystemVerilog	Verilog
	Select
	Sequential Statement
	Shared Variable
	Signal
	Signal Assignment
	Standard
	Std_Logic_1164
	String
	Subtype
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T	VHDL	SystemVerilog	Verilog
	Textio
	Type
	Type Conversion
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U	VHDL	SystemVerilog	Verilog
	Use
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V	VHDL	SystemVerilog	Verilog
	Variable
	Variable Assignment
	Vhdl 93
	Vhdl 00
	Vhdl 02
	Vhdl 08
	Vhdl 19
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W	VHDL	SystemVerilog	Verilog
	Wait
	While Loop
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X	VHDL	SystemVerilog	Verilog

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Y	VHDL	SystemVerilog	Verilog

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Z	VHDL	SystemVerilog	Verilog

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Parts not defined yet

 VHDL                    | SystemVerilog           | Verilog
-------------------------|-------------------------|-------------------------
Active Package
Actual
After
And
Anonymous
Ascending

Base
Based Literal
Binary Concatenation
Bit
Bit_Vector
Body
Boolean
Buffer
Bus

Call
Character
Choice
Clock
Close
Combinational Logic
Composite
Concurrent Signal Assignment
Condition
Constrained Array
Constraint
Constraint Violation
Context Clause
Conversion Function If

Decimal Attribute Name
Declarative Region
Delay
Delayed
Delta Textio
Design Entity
Design Unit
Don't Care
Driver Finite State Machine
Driving

Elaboration
Else
Elsif
Endfile
Event
Examples
Exponent
Expression
Extended Identifier

Falling_Edge
File (Vhdl)
Flipflop
For Name
Foreign
Formal Process

Guarded

Hexadecimal
High Attribute Name

Identifer
Image
Impure
In
Incomplete Assignment
Incomplete Type
Index Constraint
Indexed Name
Indication
Inertial
Initialization
Inout
Input
Instance_Name

Last_Active
Last_Event
Last_Value
Latch
Left Variable
Length Octal
Library Unit
Line
Linkage
Literal
Low

Mod
Mode

Nand
Natural
Nor Generate
Now Entity

Object
Open
Or
Others
Out
Output
Overloading

Package Body
Parameter
Passive Process
Path_Name
Pitfalls
Pos
Positive Report
Postponed Reset
Precedence Coding Standards
Pred Data Type
Process
Pure

Quiet

Read
Real
Register Transfer Level
Register
Reject
Rem
Resolution
Reverse_Range
Right
Rising_Edge
Rol
Ror

Selected Name
Sensitivity List
Severity
Signature
Signed
Simple_Name Select
Simulation Cycle
Sla
Slice
Sll
Speed Of Simulation
Sra
Srl
Stable
Static
Std
Std_Logic
Std_Match
Subprogram Use
Succ

Target
Test Bench
Time
To_Integer
Transaction
Transport

Unaffected
Unconstrained Array
Units
Unsigned
Until

Val
Value
Visibility

When
With
Work
Write

Xnor
Xor

Keywords taken from another online VHDL guide, for inspiration

 VHDL                    | SystemVerilog           | Verilog
-------------------------|-------------------------|-------------------------
Access Type
Aggregate
Alias
 Allocator
Architecture
Array
Assertion Statement
Attributes (predefined)
Attributes (user-defined)

Bit
Bit_Vector
Block Statement
Boolean

Case Statement
Character Type
Component Declaration
Component Instantiation
Composite Type
Concatenation
Configuration Declaration
Configuration Specification
Constant

Delay
Driver

Entity
Enumeration Type
Event
Exit Statement
Expression

File Declaration
File Type
Floating Point Type
Function

Generate Statement
Generic
Group
Guard

Identifier
If Statement
Integer Type

Library Clause
Literal
Loop Statement

Name
Next Statement
Null Statement

Operator Overloading
Operators

Package
Package Body
Physical Type
Port
Procedure
Process Statement

Range
Record Type
Report Statement
Reserved Word
Resolution Function
Resume
Return Statement

Scalar Type
Sensitivity List
Signal Assignment
Signal Declaration
Slice
Standard Package
Std_Logic
Std_Logic_1164 Package
Std_Logic_Vector
String
Subtype
Suspend

Testbench
Type
Type Conversion

Use Clause

Variable Assignment
Variable Declaration
Vector
VITAL

Wait Statement
Waveform

 SystemVerilog           | Verilog                 | VHDL
-------------------------|-------------------------|-------------------------
--AAAAAA--
                                                     access type
                                                     aggregate
alias                                                alias
                                                     allocator
                           always
always_comb
always_ff
always_latch
                           and
                                                     architecture
                                                     array
assert                                               assertion statement
                           assign
assume
                                                     attributes (predefined)
                                                     attributes (user-defined)
                           automatic
--BBBBBB--
before
                           begin
bind
bins
binsof
bit                                                  bit
                                                     bit_vector
                                                     block statement
                                                     boolean
break
                           buf
                           bufif0
                           bufif1
byte
--CCCCCC--
                           case
                           casex
                           casez
                           cell
chandle
                           class
clocking
                           cmos
                           config
const
constraint
context
continue
cover
covergroup
coverpoint
cross
                           deassign
                           default
                           defparam
                           design
                           disable
dist
do
                           edge
                           else
                           end
                           endcase
endclass
endclocking
                           endconfig
                           endfunction
                           endgenerate
endgroup
endinterface
                           endmodule
endpackage
                           endprimitive
endprogram
endproperty
                           endspecify
endsequence
                           endtable
                           endtask
enum
                           event
expect
export
extends
extern
final
first_match
                           for
                           force
foreach
                           forever
                           fork
forkjoin
                           function
                           generate
                           genvar
                           highz0
                           highz1
                           if
                           iff
                           ifnone
ignore_bins
illegal_bins
import
                           incdir
                           include
                           initial
                           inout
                           input
inside
                           instance
int
                           integer
interface
intersect
                           join
join_any
join_none
                           large
                           liblist
                           library
local
                           localparam
logic
longint
                           macromodule
matches
                           medium
modport
                           module
                           nand
                           negedge
new
                           nmos
                           nor
                           noshowcancelled
                           not
                           notif0
                           notif1
                           null
                           or
                           output
package
packed
                           parameter
                           pmos
                           posedge
                           primitive
priority
program
property
protected
                           pull0
                           pull1
                           pulldown
                           pullup
                           pulsestyle_onevent
                           pulsestyle_ondetect
pure
rand
randc
randcase
randsequence
                           rcmos
                           real
                           realtime
ref
                           reg
                           release
                           repeat
return
                           rnmos
                           rpmos
                           rtran
                           rtranif0
                           rtranif1
                           scalared
sequence
shortint
shortreal
                           showcancelled
                           signed
                           small
solve
                           specify
                           specparam
static
string
                           strong0
                           strong1
struct
super
                           supply0
                           supply1
                           table
tagged
                           task
this
throughout
                           time
timeprecision
timeunit
                           tran
                           tranif0
                           tranif1
                           tri
                           tri0
                           tri1
                           triand
                           trior
                           trireg
type
typedef
union
unique
                           unsigned
                           use
                           uwire
var
                           vectored
virtual
void
                           wait
wait_order
                           wand
                           weak0
                           weak1
                           while
wildcard
                           wire
with
within
                           wor
                           xnor
                           xor

Contents

Introduction

Using this Guide

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog

VHDL

SystemVerilog

Verilog