Return to HDL info page. Verilog Reference Guide (last edit: 27. November 2024)
Contents
Introduction
Verilog is a hardware description language (HDL) that is used to describe digital systems and circuits in the form of code. It was developed by Gateway Design Automation in the mid-1980s and later acquired by Cadence Design Systems.
Verilog is widely used for design and verification of digital and mixed-signal systems, including both application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs). It supports a range of levels of abstraction, from structural to behavioral, and is used for both simulation-based design and synthesis-based design.
The language is used to describe digital circuits hierarchically, starting with the most basic elements such as logic gates and flip-flops and building up to more complex functional blocks and systems. It also supports a range of modeling techniques, including gate-level, RTL-level, and behavioral-level modeling.
Using this Guide
A Brief Introduction to Verilog
Alphabetical Reference

A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

A
Alias
Always
Always_Comb
Always_FF
Always_Latch
And
Array
Assert
Assign
Assume
Automatic
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B
Before
Begin
Bind
Bins
Binsof
Bit
Blocking/Non-blocking
Break
Buf
BufIf0
BufIf1
Byte
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C
Case
CaseX
CaseZ
Cell
Chandle
Class
Clocking
CMOS
Conditional Assignment
Config
Const
Constraint
Context
Continue
Cover
CoverGroup
CoverPoint
Cross
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D
Deassign
Default
DefParam
Design
Disable
Dist
Do
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E
Edge
Else
End
EndCase
EndClass
EndClocking
EndConfig
EndFunction
EndGenerate
EndGroup
EndInterface
EndModule
EndPackage
EndPrimitive
EndProgram
EndProperty
EndSpecify
EndSequence
EndTable
EndTask
Enum
Event
Expect
Export
Extends
Extern
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F
Final
First_Match
For
Force
ForEach
Forever
Fork
Fork - Join
Function
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G
Generate
Genvar
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H
HighZ0
HighZ1
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I
If
Iff
IfNone
Ignore_Bins
Illegal_Bins
Import
IncDir
Include
Initial
InOut
Input
Inside
Instance
Int
Integer
Interface
InterSect
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J
Join
Join_any
Join_none
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K
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L
Large
LibList
Library
Local
LocalParam
Logic
LongInt
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M
MacroModule
Matches
Medium
ModPort
Module
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N
NAND
NegEdge
New
NMOS
NOR
NoShowCancelled
NOT
NotIf0
NotIf1
NULL
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O
Or
Output
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P
Package
Packed
Parameter
PMOS
PosEdge
Primitive
Priority
Program
Property
Protected
Pull0
Pull1
PullDown
PullUp
PulseStyle_OnEvent
PulseStyle_OnDetect
Pure
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Q
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R
Rand
RandC
RandCase
RandSequence
RCMOS
Real
RealTime
Ref
Reg
Release
Repeat
Return
RNMOS
RPMOS
RTran
RTranIf0
RTranIf1
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S
Scalared
Sequence
ShortInt
ShortReal
ShowCancelled
Signed
Small
Solve
Specify
SpecParam
Static
String
Strons0
Strong1
Struct
Super
Supply0
Supply1
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T
Table
Tagged
Task
This
Throughout
Time
TimePrecision
TimeUnit
Tran
TranIf0
TranIf1
Tri
Tri0
Tri1
TriAnd
TriOr
TriReg
Type
TypeDef
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U
Union
Unique
Unsigned
Use
Uwird
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V
Var
Vectored
Virtual
Void
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W
W
W
W
W
W
W
W
W
W
W
W
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X
XNOR
XOR
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Y
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Z