• Introduction
• Using this Guide
• A Brief Introduction to VHDL
• Syntax Summery
• Alphabetical Reference for VHDL 2019

The VHDL Reference Guide is a compact quick reference guide to the VHDL language, its syntax, semantics, synthesis and application to hardware design.

The VHDL Reference Guide is not intended as a replacement for the IEEE Standard VHDL Language Reference Manual. Unlike that document, this Reference guide does not offer a complete, formal description of VHDL. Rather, it offers answers to the questions most often asked during the practical application of VHDL, in a convenient reference format.

Nor is The VHDL Reference Guide intended to be an introductory tutorial. Information is presented here in a terse reference format, not in the progressive and sympathetic manner necessary to learn a subject as complex as VHDL. However, acknowledging that those already familiar with computer languages may wish to use this guide as a VHDL text book, a brief informal introduction to the subject is given at the start.

The main feature of The VHDL Reference Guide is that it embodies much practical wisdom gathered over many VHDL projects. It does not only provide a handy syntax reference; there are many similar books which perform that task adequately. It also warns you of the most common language errors, gives clues where to look when your code will not compile, alerts you to synthesis issues, and gives advice on improving your coding style.

The main body of this guide is organised alphabetically. Each section is indexed by a key term which appears prominently at the top of each page. Often you can find the information you want by flicking through the guide looking for the appropriate key term.

Most of the information in this guide is organised around the VHDL syntax headings, but there are additional special sections on Coding Standards, Design Flow, Errors, Reserved Words and VHDL 93, and also listings of the standard packages Standard, TEXTIO, Std_logic_1164 and Numeric_std.

If you are new to VHDL, you should start by reading A Brief Introduction to VHDL.

The Index

Bold index entries have corresponding pages in the main alphabetical reference section. The remaining index entries are followed by a list of appropriate page references in the main alphabetical reference section, given in order of importance.

Key To Notation Used To Define VHDL Syntax

The syntax in this reference guide describes VHDL'93. The main differences between VHDL'87 and VHDL'93 can be found here.

The syntax definitions are written using the Backus-Naur-format.

Here follows a short summary of the format:

• Words written using lower-case letters and possibly one or many hyphens, are used to denote a syntactical category, for example: entity-declaration.
• Reserved words are written with bold characters, for example: entity.
• Every replacement rule contains a left hand side expression and a right hand side expression separated by the sign ��, which means �looks as� or �may be replaced with�. The left hand side of the expression is always a syntactical category and may be replaced by the right hand side of the expression.
• |, a vertical line (the pipe sign) is used to separate many mutually exclusive alternatives.
• [], square brackets surround optional things that may occur once or not at all.
• {}, braces surround optional things that may occur once, many times or not at all.
• (), parenthesis are used to clarify how and in which order a rule is evaluated.
• Reserved words and characters surrounded by apostrophes, � �, are included �as is� in the source code.
• Italicized words in the beginning of the name of a syntactical category give semantic information and have no syntactical meaning. For example entity-name-identifier is the same as identifier.

In brief, square brackets [ ] enclose optional items, three dots ... means repetition, and curly brackets { } enclose comments. ItalicNames represent parts of the syntax defined elsewhere. A full description of the notation follows:

• Curly brackets { } enclose comments that are not part of the VHDL syntax being defined, but give you further information about the syntax definition.
• Syntax enclosed in square brackets [ ] is optional (except in the definition of a signature, where square brackets are part of the VHDL syntax!)
• ... means zero or more repetitions of the preceding item or line, or means a list, as follows:
• Item ... means zero or more repetitions of the Item.
• , ... means repeat in a comma separated list (e.g. A, B, C).
• ; ... means repeat in a semicolon separated list (e.g. A;B;C).
• | ... means repeat in a bar separated list (e.g. A|B|C).

There must be at least one item in the list. There is no , ; or | at the end of the list, unless it is given explicitly (as in ; ... ; ).

Underlined syntax belongs to the VHDL'93 language, but not to VHDL'87. (For the sake of clarity, underlining has been omitted where words contain the underscore character.) words in lower case letters are reserved words, built into the VHDL language (e.g. entity)

Capitalised Words (not in italics) are VHDL identifiers, i.e. user defined or pre-defined names that are not reserved identifiers (e.g. TypeName, BlockLabel).

Italic Words are syntactic categories, i.e. the name of a syntax definition given in full elsewhere. A syntactic category can be either defined on the same page, defined on a separate page, or one of the two special categories defined below.

• Italics = indicates a syntactic category which is defined and used on the same page.

Special syntactic categories:

• SomethingExpression = Expression, where the Something gives information about the meaning of the expression (e.g. TimeExpression).
• Condition = Expression, where the type of the expression is Boolean.

Background

The letters VHDL stand for the VHSIC (Very High Speed Integrated Circuit) Hardware Description Language. VHDL is a language for describing the behaviour and structure of electronic circuits, and is an IEEE standard (1076).

VHDL is used to simulate the functionality of digital electronic circuits at levels of abstraction ranging from pure behaviour down to gate level, and is also used to synthesize (i.e. automatically generate) gate level descriptions from more abstract (Register Transfer Level) descriptions. VHDL is commonly used to support the high level design (or language based design) process, in which an electronic design is verified by means of thorough simulation at a high level of abstraction before proceeding to detailed design using automatic synthesis tools.

VHDL became an IEEE standard in 1987, and this version of the language has been widely used in the electronics industry and academia. The standard was revised in 1993 to include a number of significant improvements.

The Language

In this section as in the rest of the guide, words given in Capitalised Italics are technical terms whose definitions may be found in the main body of this guide.

An hierarchical portion of a hardware design is described in VHDL by an Entity together with an Architecture. The Entity defines the interface to the block of hardware (i.e. the inputs and outputs), whilst the Architecture defines its internal structure or behaviour. An Entity may possess several alternative Architectures.

Hierarchy is defined by means of Components, which are analogous to chip sockets. A Component is Instantiated within an Architecture to represent a copy of a lower level hierarchical block. The association between the Instance of the Component and the lower level Entity and Architecture is only made when the complete design hierarchy is assembled before simulation or synthesis (analogous to plugging a chip into a chip socket on a printed circuit board). The selection of which Entity and Architecture to use for each Component is made in the Configuration, which is like a parts list for the design hierarchy.

The structure of an electronic circuit is described by making Instances of Components within an Architecture, and connecting the Instances together using Signals. A Signal represents an electrical connection, a wire or a bus. A Port Map is used to connect Signals to the Ports of a Component Instantiation, where a Port represents a pin.

Each Signal has a Type, as does every value in VHDL. The Type defines both a set of values and the set of operations that can be performed on those values. A Type is often defined in a Package, which is a piece of VHDL containing definitions which are common to several Entities, Architectures, Configurations or other Packages.

Individual wires are often represented as Signals of type Std_logic, which are defined in the package Std_logic_1164, another IEEE standard.

The behaviour of an electronic circuit is described using Processes (which represent the leaves in the hierarchy tree of the design). Each Process executes concurrently with respect to all other Processes, but the statements inside a process execute in sequential order and are in many ways similar to the statements in a software programming language. A Process can be decomposed into named Procedures and Functions, which can be given parameters. Common Procedures and Functions can be defined in a Package.

Compilation

VHDL source code is usually typed into a text file on a computer. That text file is then submitted to a VHDL compiler which builds the data files necessary for simulation or synthesis. The proper jargon for the steps performed by the compiler are Analysis, which checks the VHDL source for errors and puts the VHDL into a Library, and Elaboration, which links together the Entities and Architectures of the hierarchy.

library IEEE;
  use IEEE.Std_logic_1164.all;

entity EntityName is
  port (
    P1: in  std_logic;
    P2: in  std_logic;
    P3: out std_logic_vector(7 downto 0)
  );
end EntityName;

architecture ArchitectureName of EntityName is
  component ComponentName
  port (
    P1: in  std_logic;
    P2: out std_logic
  );
  end component;
  signal SignalName, SignalName2: Std_logic := 'U';
begin
  P: process (P1,P2,P3) -- Either sensitivity list or wait statements!
    variable VariableName, VarName2: Std_logic := 'U';
  begin
    SignalName <= Expression after Delay;
    VariableName := Expression;
    ProcedureCall(Param1, Param2, Param3);
    wait for Delay;
    wait until Condition;
    wait;
    if Condition then
      -- sequential statements
    elsif Condition then
      -- sequential statements
    else
      -- sequential statements
    end if;
    case Selection is
      when Choice1 =>
        -- sequential statements
      when Choice2 | Choice3 =>
        -- sequential statements
      when others =>
        -- sequential statements
    end case;
    for I in A'Range loop
      -- sequential statements
    end loop;
  end process P;
  SignalName <= Expr1 when Condition else Expr2;
  InstanceLabel: CompName port map (S1, S2);
  L2: CompName port map (P1 => S1, P2 => S2);
  G1: for I in A'Range generate
    -- concurrent statements
  end generate G1;
end ArchitectureName;

package PackName is
  type Enum is (E0, E1, E2, E3);
  subtype Int is Integer range 0 to 15;
  type Mem is array (Integer range <>) of
                     Std_logic_vector(7 downto 0);
  subtype Vec is Std_logic_vector(7 downto 0);
  constant C1: Int := 8;
  constant C2: Mem(0 to 63) := (others => "11111111");
  procedure ProcName (ConstParam : Std_logic;
                      VarParam   : out Std_logic;
               signal SigParam   : inout Std_logic);
  function "+" (L, R: Std_logic_vector)
                      return Std_logic_vector;
end PackName;

package body PackName is
  procedure ProcName (ConstParam : Std_logic;
                      VarParam   : out Std_logic;
               signal SigParam   : inout Std_logic) is
    -- declarations
  begin
    -- sequential statements
  end ProcName;

  function "+" (L, R: Std_logic_vector)
                      return Std_logic_vector is
    -- declarations
  begin
    -- sequential statements
    return Expression;
  end "+";
end PackName;

configuration ConfigName of EntityName is
  for ArchitectureName
    for Instances: ComponentName
      use LibraryName.EntityName(ArchName);
    end for;
  end for;
end ConfigName;

This quick reference syntax summary does not follow the notational conventions used in the rest of the Guide.

A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z